Understanding the Cache Hit and Miss Performance Monitoring Events and Using Them to Calculate Rates


It is generally important to analyze the cache access behavior of an application to determine whether some performance-critical pieces of code poorly utilize the cache hierarchy. Ivy Bridge and later microarchitectures offer a fairly rich set of performance monitoring events to count various cache-related events and estimate their impact on the overall execution time of the application. On Ivy Bridge, Haswell, and Broadwell, these events include the following: Continue reading


The Significance of the x86 SFENCE Instruction


The SFENCE instruction was first introduced in the Intel Pentium III (1999), AMD Athlon XP (2001), and AMD Morgan (2001). On the early AMD processors, it was part of the AMD 3DNow! Extensions instruction set. Since then, any processor that supports SSE (as indicated by the corresponding CPUID bit) also supports SFENCE. That is, there isn’t a dedicated CPUID bit for SFENCE.

Continue reading

The Significance of the x86 LFENCE Instruction

Note: SFENCE is discussed in another blog post. This post is about LFENCE.

The x86 ISA currently offers three “fence” instructions: MFENCE, SFENCE, and LFENCE. Sometimes they are described as “memory fence” instructions. In some other architectures and in the literature about memory ordering models, terms such as memory fences, store fences, and load fences are used. The terms “memory fence” and “load fence” have not been used in the Intel Manual Volume 3, but they have been used in the Intel Manual Volume 2 and in the AMD manuals a couple of times. I’ll focus in this article on “load fences”. Throughout this article, I’ll be referring to the latest Intel and AMD manuals at the time of writing this article.

The fact that the term “load fence” has been used in different ISAs, textbooks, and research papers has resulted in a critical misunderstanding of the x86 LFENCE instruction and confusion regarding what it does and how to use it. Continue reading

Defining Static Single Assignment

Most compilers convert the input source code into one or more intermediate representations (IRs) to make it easier and faster to analyze and optimize the code. Static single assignment (SSA) is a property of IRs that helps in not only simplifying the algorithms that analyze the code, but also improve their results at the same time, leading to more effective and efficient optimizations. The definition of SSA according to Wikipedia is currently as follows: Continue reading

The Art of Profiling Using Intel VTune Amplifier, Part 8 (Final)

Part 1, Part 2, and Part 3 of this series provided an introduction to profiling and showed how to setup VTune. The first optimization was discussed in Part 4, in which the number of times printf is executed is reduced. The second optimization was discussed in Part 5, in which strlen got replaced with a much cheaper alternative. The third optimization was discussed in Part 6, in which the amount of computation required to report progress is reduced. The third optimization was discussed in Part 7, in which the function do_pswd was inlined into its caller. The following chart shows by how much each optimization improved password cracking throughput. Continue reading

The Art of Profiling Using Intel VTune Amplifier, Part 7

Previous parts of this series can be found at the following links: Part 1, Part 2, Part 3, Part 4, Part 5, and Part 6.

In Part 6, execution time was improved by 14% and the password cracking throughput became around 150 million passwords per second. Recall from Part 1 that the baseline throughput was around 3 million passwords per second. We have come a long way and we can still do more with the help of VTune. Continue reading